AX2000-1CS896M datasheet(89/226 Pages) ACTEL

89 / 226 page

Axcelerator Family FPGAs

v2.7

2-75

Figure 2-60 • RAM Read Timing Waveforms

Table 2-88 • One RAM Block

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Mode

tWDASU

Write Data Setup vs. WCLK

1.08

1.23

1.45

tWDAHD

Write Data Hold vs. WCLK

0.22

0.25

0.30

tWADSU

Write Address Setup vs. WCLK

1.08

1.23

1.45

tWADHD

Write Address Hold vs. WCLK

0.22

0.25

0.30

tWENSU

Write Enable Setup vs. WCLK

1.08

1.23

1.45

tWENHD

Write Enable Hold vs. WCLK

0.22

0.25

0.30

tWCKH

WCLK Minimum High Pulse Width

0.98

1.11

1.31

tWCLK

WCLK Minimum Low Pulse Width

1.15

1.30

1.53

tWCKP

WCLK Minimum Period

2.29

2.61

3.07

Read Mode

tRADSU

Read Address Setup vs. RCLK

0.81

0.92

1.08

tRADHD

Read Address Hold vs. RCLK

0.00

tRENSU

Read Enable Setup vs. RCLK

0.81

0.92

1.08

tRENHD

Read Enable Hold vs. RCLK

0.00

tRCK2RD1

RCLK-To-OUT (Pipelined)

1.39

1.59

1.86

tRCK2RD2

RCLK-To-OUT (Non-Pipelined)

2.62

2.98

3.5

tRCLKH

RCLK Minimum High Pulse Width

1.00

1.14

1.34

tRCLKL

RCLK Minimum Low Pulse Width

1.21

1.38

1.62

tRCKP

RCLK Minimum Period

2.42

2.76

3.24

RCLK

RA<11:0>, REN<4:0>

RD <35:0>

tRxxSU tRxxHD

tRCKP

tRCKH

tRCKL

tRCK2RD1

tRCK2RD2

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