AX2000-1CS896M datasheet(83/226 Pages) ACTEL

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Axcelerator Family FPGAs

v2.7

2-69

Sample Implementations

Frequency Synthesis

Figure 2-53 illustrates an example where the PLL is used

to multiply a 155.5 MHz external clock up to 622 MHz.

Note that the same PLL schematic could use an external

350 MHz clock, which is divided down to 155 MHz by the

FPGA internal logic.

Figure 2-54 illustrates the PLL using both dividers to

synthesize a 133 MHz output clock from a 155 MHz input

reference clock. The input frequency of 155 MHz is

multiplied by 6 and divided by 7, giving a CLK1 output

frequency of 132.86 MHz. When dividers are used, a

given ratio can be generated in multiple ways, allowing

the user to stay within the operating frequency ranges of

the PLL.

Figure 2-53 • Using the PLL 155.5 MHz In, 622 MHz Out

Figure 2-54 • Using the PLL 155 MHz In, 133 MHz Out

Delay Line

PLL

Delay Line

RefCLK

CLK1

PowerDown

Lock

CLK2

FBMuxSel

DividerI

DelayLine

DividerJ

LowFreq

Osc

÷4

155.5 MHz

622 MHz

/i Delay

Match

/j Delay

Match

Delay Line

PLL

Delay Line

RefCLK

CLK1

PowerDown

Lock

CLK2

FBMuxSel

DividerI

DelayLine

DividerJ

LowFreq

Osc

÷6

155 MHz

132.8 MHz

155 MHz

930 MHz

Yes

/i Delay

Match

/j Delay

Match

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