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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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AX2000-1CS896PP Folha de dados(PDF) 56 Page - Actel Corporation |
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AX2000-1CS896PP Folha de dados(HTML) 56 Page - Actel Corporation |
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56 / 226 page  Axcelerator Family FPGAs 2- 42 v2.7 Timing Characteristics Table 2-60 • LVPECL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C '–2' Speed '–1' Speed 'Std' Speed Parameter Description Min. Max. Min. Max. Min. Max. Units LVPECL Output Module Timing tDP Input Buffer 1.70 1.93 2.28 ns tPY Output Buffer 2.28 2.60 3.06 ns tICLKQ Clock-to-Q for the I/O input register 0.67 0.77 0.90 ns tOCLKQ Clock-to-Q for the IO output register and the I/O enable register 0.67 0.77 0.90 ns tSUD Data Input Set-Up 0.23 0.27 0.31 ns tSUE Enable Input Set-Up 0.26 0.30 0.35 ns tHD Data Input Hold 0.00 0.00 0.00 ns tHE Enable Input Hold 0.00 0.00 0.00 ns tCPWHL Clock Pulse Width High to Low 0.43 0.48 0.57 ns tCPWLH Clock Pulse Width Low to High 0.45 0.51 0.60 ns tWASYN Asynchronous Pulse Width 0.43 0.48 0.57 ns tREASYN Asynchronous Recovery Time 0.10 0.10 0.10 ns tHASYN Asynchronous Removal Time 0.00 0.00 0.00 ns tCLR Asynchronous Clear-to-Q 0.23 0.27 0.31 ns tPRESET Asynchronous Preset-to-Q 0.23 0.27 0.31 ns |
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