AX2000-1CS896PP datasheet(49/226 Pages) ACTEL

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Axcelerator Family FPGAs

v2.7

2-35

SSTL2

Stub Series Terminated Logic for 2.5V is a general-purpose 2.5V memory bus standard (JESD8-9). The Axcelerator

devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output

buffer.

Class I

AC Loadings

Timing Characteristics

Table 2-43 • DC Input and Output Levels

VIL

VIH

VOL

VOH

IOL

IOH

Min,V

Max,V

Min,V

Max,V

Min,V

-0.3

VREF-0.2

VREF+0.2

3.6

VREF-0.57

VREF+0.57

7.6

-7.6

Figure 2-21 • AC Test Loads

Table 2-44 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

Cload (pF)

VREF-0.75

VREF+0.75

VREF

1.25

* Measuring Point = Vtrip

Test Point

30 pF

VTT

Table 2-45 • 2.5V SSTL2 Class I I/O Module

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

2.5V SSTL2 Class I I/O Module Timing

tDP

Input Buffer

1.86

2.12

2.50

tPY

Output Buffer

2.43

2.76

3.25

tICLKQ

Clock-to-Q for the I/O input register

0.67

0.77

0.90

tOCLKQ

Clock-to-Q for the IO output register and the I/O

enable register

0.67

0.77

0.90

tSUD

Data Input Set-Up

0.23

0.27

0.31

tSUE

Enable Input Set-Up

0.26

0.30

0.35

tHD

Data Input Hold

0.00

tHE

Enable Input Hold

0.00

tCPWHL

Clock Pulse Width High to Low

0.43

0.48

0.57

tCPWLH

Clock Pulse Width Low to High

0.45

0.51

0.60

tWASYN

Asynchronous Pulse Width

0.43

0.48

0.57

tREASYN

Asynchronous Recovery Time

0.10

tHASYN

Asynchronous Removal Time

0.00

tCLR

Asynchronous Clear-to-Q

0.23

0.27

0.31

tPRESET

Asynchronous Preset-to-Q

0.23

0.27

0.31

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