Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

Preview PDF HTML

PSD913F2 Folha de dados(PDF) 76 Page - STMicroelectronics

Nome de Peças PSD913F2
Descrição Electrónicos  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  91 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD913F2 Folha de dados(HTML) 76 Page - STMicroelectronics

Back Button PSD913F2 Datasheet HTML 72Page - STMicroelectronics PSD913F2 Datasheet HTML 73Page - STMicroelectronics PSD913F2 Datasheet HTML 74Page - STMicroelectronics PSD913F2 Datasheet HTML 75Page - STMicroelectronics PSD913F2 Datasheet HTML 76Page - STMicroelectronics PSD913F2 Datasheet HTML 77Page - STMicroelectronics PSD913F2 Datasheet HTML 78Page - STMicroelectronics PSD913F2 Datasheet HTML 79Page - STMicroelectronics PSD913F2 Datasheet HTML 80Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 76 / 91 page
background image
PSD935G2
PSD9XX Family
75
-90
-12
Turbo
Symbol
Parameter
Conditions
Min
Max
Min
Max
Off
Unit
tLVLX
ALE or AS Pulse Width
22
24
ns
tAVLX
Address Setup Time
(Note 3)
7
9
ns
tLXAX
Address Hold Time
(Note 3)
8
10
ns
tAVQV
Address Valid to Data Valid
(Note 3)
90
120
Add 20**
ns
t SLQV
CS Valid to Data Valid
90
120
ns
RD to Data Valid
(Note 5)
35
35
ns
t RLQV
RD or PSEN to Data Valid,
80C51 Mode
(Note 2)
45
48
ns
t RHQX
RD Data Hold Time
(Note 1)
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
36
40
ns
tRHQZ
RD to Data High-Z
(Note 1)
38
40
ns
tEHEL
E Pulse Width
38
42
ns
tTHEH
R/W Setup Time to Enable
10
16
ns
tELTL
R/W Hold Time After Enable
0
0
ns
tAVPV
Address Input Valid to
(Note 4)
30
35
ns
Address Output Delay
Read Timing (3.0 V to 3.6 V Versions)
Microcontroller Interface – PSD935G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
NOTES: 1. RD timing has the same timing as DS and PSEN signals.
2. RD and PSEN have the same timing for 80C51.
3. Any input used to select an internal PSD4135G2V function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS signals.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91


Folha de dados Download

Go To PDF Page


Ligação URL



ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   Link para a ficha técnica    |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com