SH7708 datasheet(180/633 Pages) RENESAS

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9.3

Clock Operating Modes

Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the

clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes.

Table 9.3

Clock Operating Modes

Pin Values

Clock I/O

PLL2

Div-

PLL1

Divider 1 Divider 2 CKIO

ModeMD2 MD1 MD0 Source Output

On/Off ider 3 On/Off Input

Input

Frequency

EXTAL CKIO

multi-

plication

ratio: 1

Off

PLL1

output

PLL1

(EXTAL)

EXTAL CKIO

multi-

plication

ratio: 4

Off

PLL1

output

PLL1

(EXTAL)

× 4

Crystal

oscillator

CKIO

multi-

plication

ratio: 4

Off

PLL1

output

PLL1

(Crystal)

× 4

EXTAL CKIO

multi-

plication

ratio: 1

Off

(initial

value)

PLL2

output

PLL2

(EXTAL)

× 1

PLL1

output

Crystal

oscillator

CKIO

multi-

plication

ratio: 1

Off

(initial

value)

PLL2

output

PLL2

(Crystal)

× 1

PLL1

output

CKIO

—

Off

PLL1

output

PLL1

(CKIO)

Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by

PLL circuit 2 before being supplied inside the SH7708 Series. PLL circuit 1 is constantly on, and

there are no frequency range restrictions compared to mode 3. An input clock frequency of 8 MHz

to 60 MHz(SH7708, SH7708S) or 16 MHz to 60 MHz(SH7708R) can be used, and the CKIO

frequency range is 8 MHz to 60 MHz(SH7708, SH7708S) or 16 MHz to 60 MHz(SH7708R).

As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for

connection of synchronous DRAM.

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