SH7018 datasheet(82/431 Pages) RENESAS

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6.3

Description of Registers

6.3.1

Interrupt Priority Registers A to H (IPRA to IPRH)

Interrupt priority registers A to H (IPRA to IPRH) are 16-bit readable/writable registers that set

priority levels from 0 to 15 for IRQ interrupts and on-chip peripheral module interrupts.

Correspondence between interrupt request sources and each of the IPRA to IPRH bits is shown in

table 6.4.

Bit:

Initial value:

R/W:

R/W

Bit:

Initial value:

R/W:

R/W

Table 6.4

Interrupt Request Sources and IPRA to IPRH

Bits

15 to 12

11 to 8

7 to 4

3 to 0

Interrupt priority register A

IRQ0

IRQ1

IRQ2

IRQ3

Interrupt priority register B

Reserved

IRQ6

IRQ7

Interrupt priority register C

Reserved

Interrupt priority register D

MTU0

MTU1

Interrupt priority register E

MTU2

MTTU2

Reserved

Interrupt priority register F

Reserved

SCI1

Interrupt priority register G

A/D

Reserved

CMT0

CMT1

Interrupt priority register H

WDT, TIM2

Reserved

As indicated in table 6.4, four

IRQ pins or groups of 4 on-chip peripheral modules are allocated to

each register. Each of the corresponding interrupt priority ranks are established by setting a value

from H'0 (0000) to H'F (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0.

Interrupt priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting

H'F. 8-bit timers 1 and 2 are set to the same priority rank.

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