SH-2E datasheet(93/1042 Pages) RENESAS

93 / 1042 page

1. Overview

Rev.3.00 Mar. 12, 2008 Page 3 of 948

REJ09B0177-0300

Item

Features

Clock pulse generator

(CPG/PLL)

• On-chip clock pulse generator (maximum operating frequency: 80 MHz)

• Independent generation of CPU system clock and peripheral clock for peripheral modules

• On-chip clock-multiplication PLL circuit (×8)

• Internal clock frequency range: 5 to 10 MHz

Interrupt controller (INTC)

• Nine external interrupt pins (NMI,

IRQ0 to IRQ7)

• 123 internal interrupt sources

(ATU-II

× 75, SCI × 20, DMAC × 4, A/D × 5, WDT × 1, UBC × 1, CMT × 2, HCAN-II × 8, H-

UDI

× 1, SSU* × 6 )

• 16 programmable priority levels

User break controller

(UBC)

• Requests an interrupt when the CPU or DMAC generates a bus cycle with specified

conditions (interrupt can also be masked)

• Trigger pulse output (UBCTRG) on break condition

⎯ Selection of trigger pulse width (φ ×1, ×4, ×8, ×16)

• Simplifies configuration of an on-chip debugger

Bus state controller (BSC)

• Supports external memory access (SRAM and ROM directly connectable)

⎯

8/16-bit bus space

• 3.3 V bus interface

• 16 MB address space divided into four areas, with the following parameters settable for

each area:

⎯ Bus size (8 or 16 bits)

⎯ Number of wait cycles

⎯ Chip select signals (

CS0 to CS3) output for each area

• Wait cycles can be inserted using an external

WAIT signal

• External access in minimum of two cycles

• Provision for idle cycle insertion to prevent bus collisions

Direct memory access

controller (DMAC)

(4 channels)

• DMA transfer possible for the following devices:

⎯ External memory, on-chip memory, on-chip peripheral modules (excluding DMAC, UBC,

BSC)

• DMA transfer requests by on-chip modules

⎯ SCI, A/D converter, ATU-II, HCAN-II, SSU*

• Cycle steal or burst mode transfer

• Dual address mode

⎯ Direct transfer mode

⎯ Indirect transfer mode (channel 3 only)

• Address reload function (channel 2 only)

• Transfer data width: Byte/word/longword

Note:

SSU: Synchronous Serial Communication Unit

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