SH-2E datasheet(39/1042 Pages) RENESAS

39 / 1042 page

Differences between SH7058 and SH7058S/SH7059

Rev.3.00 Mar. 12, 2008 Page xxxix of xc

REJ09B0177-0300

SH7058 (Rev.3, REJ09B0046-0300H)

SH7058S/SH7059

22.3 Port B

Figure 22.2 Port B

806

PB15 (I/O) / PULS5 (output) / SCK2 (I/O)

PB13 (I/O) / SCK0 (I/O)

23.3 Port B

Figure 23.2 Port B

Figure amended

PB15 (I/O) / PULS5 (output) / SCK2 (I/O) / SSCK1 (output)

PB13 (I/O) / SCK0 (I/O) / SSCK0 (output)

22.3.1 Register Configuration

Table 22.3 Register Configuration

806

Note: Register access with an internal clock multiplication

ratio of 4 requires four or five internal clock (

φ) cycles.

23.3.1 Register Configuration

Table 23.3 Register Configuration

Note deleted

22.3.2 Port B Data Register (PBDR)

807

Bits PB15DR to PB0DR correspond to pins

PB15/PULS5/SCK2 to PB0/TO6A.

…PBDR is initialized to H'0000 by a power-on reset

(excluding a WDT power-on reset), and in hardware

standby mode. It is not initialized in software standby mode

or sleep mode.

23.3.2 Port B Data Register (PBDR)

Description amended

Bits PB15DR to PB0DR correspond to pins

PB15/PULS5/SCK2/SSCK1 to PB0/TO6A.

…PBDR is initialized to H'0000 by a power-on reset

(excluding a WDT power-on reset), in hardware standby

mode, and in software standby mode. It is not initialized in

sleep mode.

22.3.3 Port B Port Register (PBPR)

808

Bits PB15PR to PB0PR correspond to pins

PB15/PULS5/SCK2 to PB0/TO6A.

23.3.3 Port B Port Register (PBPR)

Description amended

Bits PB15PR to PB0PR correspond to pins

PB15/PULS5/SCK2/SSCK1 to PB0/TO6A.

22.4 Port C

Figure 22.3 Port C

808

PC3 (I/O) / RxD2 (input)

PC2 (I/O) / TxD2 (output)

23.4 Port C

Figure 23.3 Port C

Figure amended

PC3 (I/O) / RxD2 (input) / SSI1 (input)

PC2 (I/O) / TxD2 (output) / SSO1 (output)

22.4.1 Register Configuration

Table 22.5 Register Configuration

808

Note: Register access with an internal clock multiplication

ratio of 4 requires four or five internal clock (

φ) cycles.

23.4.1 Register Configuration

Table 23.5 Register Configuration

Note deleted

22.4.2 Port C Data Register (PCDR)

809

PCDR is initialized to H'0000 by a power-on reset

(excluding a WDT power-on reset), and in hardware

standby mode. It is not initialized in software standby mode

or sleep mode.

23.4.2 Port C Data Register (PCDR)

Description amended

PCDR is initialized to H'0000 by a power-on reset

(excluding a WDT power-on reset), in hardware standby

mode, and in software standby mode. It is not initialized in

sleep mode.

22.5.1 Register Configuration

Table 22.7 Register Configuration

810

Note: Register access with an internal clock multiplication

ratio of 4 requires four or five internal clock (

φ) cycles.

23.5.1 Register Configuration

Table 23.7 Register Configuration

Note deleted

SH-2E Folha de dados(PDF) 39 Page - Renesas Technology Corp

SH-2E Folha de dados(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL