M32CSLASH8B datasheet(268/406 Pages) RENESAS

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M32C/8B Group

18. A/D Converter

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 251 of 385

18. A/D Converter

M32C/8B Group has one 10-bit successive approximation A/D converter with a capacitance coupled amplifier.

The results of A/D conversion are stored into the AD0i registers (i = 0 to 7) corresponding to the selected pins. When

using DMAC operating mode, the conversion results are stored only into the AD00 register.

Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures

18.2 to 18.6 show registers associated with the A/D converter.

Table 18.1

A/D Converter Specifications

NOTES:

1. The

φAD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5 V.

The

φAD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5 V.

Without the sample and hold function, the

φAD frequency must be 250 kHz or higher.

With the sample and hold function, the

φAD frequency must be 1 MHz or higher.

2. AVCC = VCC1

≥ VCC2

AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1)

≤ VCC1,

AD input (AN0_0 to AN0_7, AN2_0 to AN2_7)

≤ VCC2

Item

Specification

A/D conversion method

Successive approximation (with capacitance coupled amplifier)

Analog input voltage

0 V to AVCC (VCC1)

Operating clock

φAD(1)

fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8

Resolution

Selectable from 8 bits or 10 bits

Operating modes

• One-shot mode

• Repeat mode

• Single sweep mode

• Repeat sweep mode 0

• Repeat sweep mode 1

• Multi-port single sweep mode

• Multi-port repeat sweep mode 0

Analog input pins(2)

144 pin package: 34 pins

8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7),

AN2 (AN2_0 to AN2_7), and AN15 (AN15_0 to AN15_7)

2 extended input pins (ANEX0 and ANEX1)

100 pin package: 26 pins

8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7),

AN2 (AN2_0 to AN2_7)

2 extended input pins (ANEX0 and ANEX1)

A/D conversion start condition

• Software trigger

The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts).

• External trigger (retrigger is enabled)

When the falling edge is detected at the ADTRG pin after the ADST bit is set to 1.

• Hardware trigger (retrigger is enabled)

Timer B2 interrupt request of the three-phase motor control timer function (after

the ICTB2 register completes counting) is generated after the ADST bit is set

to 1.

Conversion rate per pin

• Without sample and hold function

8-bit resolution: 49

φAD cycles, 10-bit resolution: 59 φAD cycles

• With sample and hold function

8-bit resolution: 28

φAD cycles, 10-bit resolution: 33 φAD cycles

The 144-pin package is described as an example in this chapter.

Pins AN15_0 to AN15_7 are not provided in the 100-pin package.

NOTE

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