M32CSLASH8B datasheet(267/406 Pages) RENESAS

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M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 250 of 385

17.1.6.2 Formats

17.1.6.2.1 Direct Format

When data is transmitted, data set in the UiTB register (i = 0 to 4) is transmitted with even parity, starting from

D0. When data is received, received data is stored into the UiRB register, starting from D0. A parity error is

determined with even parity.

Set the bits as follows to transmit or receive in the direct format.

• Set the PRYE bit in the UiMR register to 1 (parity enabled).

• Set the PRY bit in the UiMR register to 1 (even parity).

• Set the UFORM bit in the UiC0 register to 0 (LSB first).

• Set the UiLCH bit in the UiC1 register to 0 (not inverted).

17.1.6.2.2 Inverse Format

When data is transmitted, values set in the UiTB register are logically inverted. The data with the inverted

values is transmitted with odd parity, starting from D7. When data is received, received data is logically

inverted to be stored into the UiRB register, starting from D7. A parity error is determined with odd parity.

Set the bits as follows to transmit or receive in the inverse format.

• Set the PRYE bit to 1 (parity enabled).

• Set the PRY bit to 0 (odd parity).

• Set the UFORM bit to 1 (MSB first).

• Set the UiLCH bit to 1 (inverted).

Figure 17.36

SIM Interface Formats

(1) Direct format

i = 0 to 4

P: Even parity

"H"

"L"

(2) Inverse format

TXDi

P: Odd parity

"H"

"L"

TXDi

ST: Start bit

SP: Stop bit

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