ADE3800SXL datasheet(33/138 Pages) STMICROELECTRONICS

Nome de Peças	ADE3800SXL

Descrição Electrónicos	Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

PDF	138 Pages

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Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

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ADE3800

4.6

Sync Retiming (SRT)

The Sync Retiming block retimes synchronization signals (e.g. HSync and VSync) into either the

XCLK or in-clock domains.

SRT provides the following:

● Retimes all sync signals going to SMEAS into the xclk domain

● Extracts vertical sync from composite sync signals

● Divides sclk by up to 1024 for activity detection purposes (SMEAS)

● Generates a delayed version of vertical sync from a mux-selectable vertical sync source

● Generates a coast signal in the xclk domain for the LLPLL

● Measures the effect of the filter on marginal composite sync signals and returns a bad_filter

flag

● Retimes horizontal and vertical syncs into the inclk domain.

4.6.1

Coast Signal

In composite or SOG sync mode, HSYNC pulses may not exist during the VSYNC pulse signal and

will cause the LLK to unlock and loose track of HSYNC signal. Coarse signal (also known as LLK

Inhibit/Free Run signal) is used to generate a vertical pulse that wraps around the incoming

VSYNC.

Coast pulse reference (0) is either edge of VSYNC, and its set and reset values are expressed in

XCLK units.

Figure 6: Vertical sync extraction and filtering

srt_vsync_sel[2]

ADE3800SXL Folha de dados(PDF) 33 Page - STMicroelectronics