ADL5321

Rev. 0 | Page 14 of 16

10µF

C1

1.0 pF

C2

10pF

10 nF

10 pF

9.5 nH

C3

1.2 pF

1

2

(2)

3

Figure 28. Evaluation Board Layout and Default Component Placement for

Operation from 2500 MHz to 2700 MHz (Note: C7 Is Not Placed)

10µF

C3

1.2 pF

C1

10 pF

C7

C2

10 pF

10 nF

10 pF

9.5 nH

1

2

(2)

3

Figure 29. Evaluation Board Layout and Component Placement for

Operation from 3400 MHz to 3850 MHz