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ST72411R Folha de dados(PDF) 20 Page - STMicroelectronics

Nome de Peças ST72411R
Descrição Electrónicos  8-BIT MCU WITH SMARTCARD INTERFACE, LCD DRIVER, 8-BIT TIMER, SAFE RESET AND SUPPLY MONITORING
PDF  71 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72411R Folha de dados(HTML) 20 Page - STMicroelectronics

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RESET MANAGER (Cont’d)
,QW
HUQDO/RZ 9 RO
W
DJ H ’ HW
HFW
LRQ 5 ( 6 ( 7
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
- LVD Power-On RESET
- Voltage Drop RESET
In the second sequence, a “delay” phase is used
to keep the device in RESET state until VDD rises
up to VIT+ (see Figure 14).
Important: if OSC_SEL pin is HIGH (external
clock selected), the LVD Power-On and the Volt-
age Drop features are disabled during the first 260
clock cycles (fCPU) after reset. This means that an
external reset circuitry must be provided to reset
the microcontroller.
Figure 14. LVD RESET Sequences when the OSC_SEL pin is tied to GND
5( 6 ( 7
581
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
32 : ( 5
RESET PIN
EXTERNAL RESET SOURCE
5( 6 ( 7
581
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
58 1
RESET PIN
EXTERNAL RESET SOURCE
9 ’’
VDDnominal
DELAY
VIT+
VIT-
9 ’’
VDDnominal
VIT+
/
9
’
3
2
:
(
5
2
1
5
(
6
(
7
9
2
/
7
$
*
(
’
5
2
3
5
(
6
(
7
2))
7KH2 6 &B6 ( / SLQ LV W
LHG W
R 9 66
LQW
HUQDOFORFN VHO
HFW
HG / 9 ’ 6 DO
ZD\V DFW
LYDW
HG
7KH2 6 &B6( / SLQ LV W
LHG W
R * 1 ’
LQW
HUQDOFORFNVHO
HFW
HG / 9 ’ 6 DO
ZD\ V DFW
LYDW
HG



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