ST6375 datasheet(40/84 Pages) STMICROELECTRONICS

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ST6365, ST6375, ST6385 ST6367, ST6377, ST6387

SERIAL PERIPHERAL INTERFACE (Cont’d)

4.3.4 STD SPI Protocol (Shift Register)

This protocol is similar to the I

2C BUS with the ex-

ception that there is no acknowledge pulse and

there are no stop or start bits. The clock cannot be

slowed down by the external peripherals.

In this case all three outputs should be high in or-

der not to lock the software I/Os from functioning.

SPI Standard Bus Protocol: The standard bus pro-

tocol is selected by loading the SPI Control Regis-

ter 1 (SCR1 Add. EBh). Bit 0 named I2C must be

set at one and bit 1 named STD must be reset.

When the standard bus protocol is selected bit 2 of

the SCR1 is meaningless.

This bit named STOP bit is used only in I

2C BUS

or SBUS. However take care that THE STOP BIT

MUST BE RESET WHEN THE STANDARD PRO-

TOCOL IS USED. This bit is set to ZERO after RE-

SET.

Figure 28. Software Bus (Hardware Bus Disabled) Timing Diagram

4.3.5 SPI Data/Control Register

For I/O details on SCL (Serial Clock), SDA (Serial

Data) and SEN (Serial Enable) please refer to I/O

Ports description with reference to the following

registers:

Port C data register, Address C2h (Read/Write).

- BIT D0 “SCL”

- BIT D1 “SDA”

- BIT D3 “SEN”

Port C data direction register, Address C6h (Read/

Write).

SPI Serial Data Register (SSDR)

Address: CCh - Read/Write

Reset Value: XXh

SSDR7-0. These are the SPI data bits. They can

be neither read nor written when SPI is operating

(BUSY bit set). They are undefined after reset.

VA00453

234

IDENT (was SEN, this is optionally controlled by software; output

as far as hardware is concerned is high).

CLOCK

(was SCL)

DATA

(was SDA, TRANSMIT)

DATA

(was SDA, RECEIVE)

SSDR

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