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PSD835G2 Folha de dados(PDF) 82 Page - STMicroelectronics

Nome de Peças PSD835G2
Descrição Electrónicos  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2 Folha de dados(HTML) 82 Page - STMicroelectronics

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PSD835G2
PSD8XX Family
81
NOTES: 1. RD timing has the same timing as DS and PSEN signals.
2. RD and PSEN have the same timing.
3. Any input used to select an internal PSD835G2 function.
4. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS.
-70
-90
Turbo
Symbol
Parameter
Conditions
Min
Max
Min
Max
Off
Unit
tLVLX
ALE or AS Pulse Width
15
20
ns
tAVLX
Address Setup Time
(Note 3)
4
6
ns
tLXAX
Address Hold Time
(Note 3)
7
8
ns
tAVQV
Address Valid to Data Valid
(Note 3)
70
90
Add 12
ns
t SLQV
CS Valid to Data Valid
75
100
ns
RD to Data Valid
(Note 5)
24
32
ns
t RLQV
RD or PSEN to Data Valid,
80C51 Mode
(Note 2)
31
38
ns
t RHQX
RD Data Hold Time
(Note 1)
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
27
32
ns
tRHQZ
RD to Data High-Z
(Note 1)
20
25
ns
tEHEL
E Pulse Width
27
32
ns
tTHEH
R/W Setup Time to Enable
6
10
ns
tELTL
R/W Hold Time After Enable
0
0
ns
tAVPV
Address Input Valid to Address
(Note 4)
20
25
ns
Output Delay
Read Timing (5 V ± 10% Versions)
Microcontroller Interface – PSD835G2 AC/DC Parameters
(5V ± 10% Versions)



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