PSD835G2 datasheet(71/110 Pages) STMICROELECTRONICS

71 / 110 page

PSD8XX Family

PSD835G2

Port E Pin

JTAG Signals

Description

PE0

TMS

Mode Select

PE1

TCK

Clock

PE2

TDI

Serial Data In

PE3

TDO

Serial Data Out

PE4

TSTAT

Status

PE5

TERR

Error Flag

Table 30. JTAG Port Signals

9.6 Programming In-Circuit using the JTAG-ISP Interface

The JTAG-ISP interface on the PSD835G2 can be enabled on Port E (see Table 30). All

memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be

programmed through the JTAG-ISC interface. A blank part can be mounted on a printed

circuit board and programmed using JTAG-ISP.

The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional

signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and

erase operations.

*SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset.

Port Configuration

Power On Reset

Warm Reset

Power Down Mode

MCU I/O

Input Mode

Unchanged

PLD Output

Valid after internal

Valid

Depend on inputs to

PSD configuration

PLD (address are

bits are loaded

blocked in PD mode)

Address Out

Tri-stated

Not defined

Data Port

Tri-stated

Peripheral I/O

Tri-stated

Table 29. Status During Power On Reset, Warm Reset and Power Down Mode

Power On Reset

Warm Reset

Power Down Mode

PMMR0, 2

Cleared to “0”

Unchanged

Micro

⇔Cells Flip

Cleared to “0” by

Depend on .re and

Flop status

internal power on

.pr equations

reset

VM Register*

Initialized based on

Unchanged

the selection in

PSDsoft

Configuration Menu.

All other registers

Cleared to “0”

Unchanged

9.5.3.4 Reset of Flash Erase and Programming Cycles

An external reset on the RESET pin will also reset the internal Flash memory state

machine. When the Flash is in programming or erase mode, the RESET pin will terminate

the programming or erase operation and return the Flash back to read mode in tNLNH-A

(minimum 25 µs) time.

By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E

are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.

See ST Application Note AN1153 for more details on JTAG In-System-Programming.

The

PSD835G2

Functional

Blocks

(cont.)

PSD835G2 Folha de dados(PDF) 71 Page - STMicroelectronics

PSD835G2 Folha de dados(HTML) 71 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL