R5F526TACDFM datasheet(2/142 Pages) RENESAS

2 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 2 of 142

Oct 31, 2024

RX26T Group

1. Overview

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different

packages.

Table 1.1 shows the outline of maximum specifications. The peripheral functions and the number of their channels vary

depending on the number of pins of the package, and the RAM capacity. For details, see Table 1.2, Comparison of

Functions for Different Packages.

Table 1.1

Outline of Specifications (1/9)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 120 MHz

 32-bit RX CPU (RXv3)

 Minimum instruction execution time: One instruction per state (cycle of the system clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 113 instructions (products with 64 Kbytes of RAM), 111 instructions (products with 48

Kbytes of RAM)

Standard provided instructions: 111

Basic instructions: 77

Single precision floating point instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2 (only supported by products with 64 Kbytes

of RAM)

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32/32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single-precision (32-bit) floating-point number

 Data types and floating-point exceptions in conformance with the IEEE754 standard

function

 Fast collective saving and restoration of the values of CPU registers

 16 save register banks

Memory

Code flash memory

 Capacity: 512 Kbytes, 256 Kbytes, 128 Kbytes

 120 MHz No-wait access

 On-board programming: Three types

 Instructions are executable only for the program stored in the TM target area by using the

Trusted Memory (TM) function and protection against data reading is realized.

 A dual-bank structure allows programming during reading or exchanging the start-up

areas

Data flash memory

 Capacity: 16 Kbytes

 Programming/erasing: 100,000 times

Unique ID

 12-byte unique ID for the device

RAM

 Capacity: 64 Kbytes, 48 Kbytes

 120 MHz No-wait access

 SED (single error detection)

Operating modes

 Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (SCI interface)

Boot mode (FINE interface)

 Selection of operating mode by register setting

Single-chip mode

 Endian selectable

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