R5F526TACDFM datasheet(82/142 Pages) RENESAS

82 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 82 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

2.4.5.4

POE3

Note 1. tPBcyc: PCLKB cycle

Figure 2.18

POE Input Timing

Figure 2.19

Output Disable Time for POE in Response to Transition of the POEn# Signal Level

Table 2.26

POE3 Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Typ.

Max.

Unit*1

Test Conditions

POE

POEn# input pulse width

(n = 0, 4, and 8 to 12)

tPOEW

1.5

—

tPBcyc Figure 2.18

Output disable time

Transition of the POEn#

signal level

tPOEDI

—

5 PCLKB + 0.24

µs

Figure 2.19

When detecting falling edges

(ICSRm.POEnM[3:0] = 0000

(m = 1 to 8, n = 0, 4, 8 to 12))

Simultaneous conduction

of output pins

tPOEDO

—

3 PCLKB + 0.2

µs

Figure 2.20

Detection of comparator

outputs

tPOEDC

—

5 PCLKB + 0.2

µs

Figure 2.21

The time is that when the noise

filter for comparator C is not in

use (CMPCTL.CDFS[1:0] = 00)

and excludes the time for

detection by comparator C.

tPOEDS

—

1 PCLKB + 0.2

µs

Figure 2.22

Time for access to the register is

not included.

Oscillation stop detection

tPOEDOS

—

µs

Figure 2.23

POEn# input

(n = 0, 4, 8 to 12)

PCLKB

tPOEW

POEn# input

(n = 0, 4, 8 to 12)

MTU PWM output pins

GPTW PWM output pins

Outputs disabled

tPOEW

tPOEDI

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