R7KA8M2AFDCAM datasheet(74/295 Pages) RENESAS

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Table 2.28

Current of high-speed mode, CPU0 Deep Sleep, CPU1 Sleep (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

125 °C

Supply

current

*1*2*3

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VSCR_1

ICC_DCDC*4

141

—

VCC_DCDC = 3.3 V

CPU0 = Deep Sleep

IDD

363

—

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*4

—

161

—

IDD

—

414

—

CPUCLK0 = 600

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*4

—

196

IDD

—

504

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VSCR_2

ICC_DCDC*4

132

157

184

IDD

347

411

481

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 3. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Table 2.29

Current of high-speed mode, CPU0 Deep Sleep, CPU1 Sleep (External VDD mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

125 °C

Supply

current

*1*2*3

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VCL = voltage

range 1

IDD

363

—

CPU0 = Deep Sleep

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VCL = voltage

range 1

IDD

—

414

—

CPUCLK0 = 600

MHz

CPUCLK1 = 200

MHz

VCL = voltage

range 1

IDD

—

504

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VCL = voltage

range 2

IDD

347

411

481

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 3. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 74 of 295

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