CSG14K_CSG8K datasheet(21/114 Pages) AMSOSRAM

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 20

7.1.4

DPP

The DPP blocks perform digital operations on the visible pixel data: digital offset, digital gain,

row noise correction.

7.1.5

Sub-LVDS Outputs

The sensor has 16 data channels to output the processed data. Every channel outputs the

data of 480 columns when reading the recommended pixel array. Multiplexing the data on

fewer outputs is supported as well.

7.1.6

Sequencer

The on-chip sequencer will generate all required control signals to operate the sensor from

only a few external control signals. This sequencer can be activated and programmed through

the SPI interface.

The sequencer includes the following features:

●

SPI protocol and register banks management.

●

Exposure and frame timing generation based on external inputs or internal settings.

●

Dual exposure HDR mode.

●

Y-windowing, Y-subsampling and binning.

●

Statistics data gathering.

7.1.7

SPI Interface

The SPI interface is used to load the on-chip registers with settings to configure the image

sensor. Features like exposure time, windowing, and subsampling are programmed using this

interface. The settings in the on-chip registers can also be read back for test and debug of the

surrounding system.

7.1.8

Temperature Sensor

Two on-chip thermal sensors are included (one on the top right side and one on the bottom

right side of the pixel array). The temperature data is read out through the SPI interface.

7.1.9

PLL

Various clock frequencies are required internally to operate the sensor. These are derived

from a single input frequency using an on-chip PLL. Through configuration over SPI, a range

of input clock frequencies is supported.

The main internal clocks are:

●

CLK_ADC is the PLL output clock and is used to operate the ADC.

●

CLK_SER is the sub-LVDS output clock (625 MHz for 1.25 Gbit/s).

●

CLK_PIX is the pixel clock and has a ratio of:

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