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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v2-01 • 2023-Feb-10

113

│ 62

alternative, the 3 different power supplies can be ramped up all together. Never ramp-up

VDD12* after the VDD33* and VDDPIX, this can leave the sensor into an unknown state.

Power-Down Sequence

Figure 66:

Power-Down Sequence

All external supplies ramp back down to 0 V following the order present in Figure 66. The

ramp-down of the analog supplies VDD33* and VDDPIX must be done before the ramp-down

of the digital supply VDD12*, in alternative, the 3 different power supplies can be ramped

down all together. Never ramp-down VDD12* before the VDD33* and VDDPIX, this can leave

the sensor into an unknown state.

Release Hard Reset

This is achieved by

changing the RST_N input from ‘0’ to ‘1’.

Assert Hard Reset

This is achieved by changing the RST_N input from ‘1’ to ‘0’.

Common Upload (1)

Independent of the sensor operation mode, a group of settings referred to as the Common

Upload (1) must be uploaded in the specified order. These settings are provided in a separate

file called CSG14K_common_upload_1.txt, where every line of that file corresponds to a

single 8-bit SPI transaction or a wait statement. The syntax for these commands is detailed

below.

Write DATA to ADDRESS

Lines starting with the write keyword indicate SPI write transactions where DATA specifies

the value to be written to ADDRESS.

Read EXPECTED from ADDRESS

Lines starting with the read keyword indicate SPI read transactions where EXPECTED is the

value that should be read from ADDRESS.

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