ST7FLCD1_05 datasheet(39/95 Pages) STMICROELECTRONICS

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ST7FLCD1

I/O Ports

7.4

Port B

Each Port B bit can be used as the Analog source to the Analog-to-Digital Converter.

Only one I/O line at a time must be configured as an analog input. Pins levels are all limited to 5V.

All unused I/O lines should be tied to an appropriate logic level (either VDD or VSS).

Since ADC and microprocessor are on the same chip and if high precision is required, the user

should not switch heavily loaded signals during conversion. Such switching will affect the supply

voltages used as analog references. The conversion accuracy depends on the quality of power

supplies (VDD and VSS). The user must take special care to ensure that a well regulated reference

voltage is present on pins VDD and VSS (power supply variations must be less than 3.3 V/ms). This

implies, in particular, that a suitable decoupling capacitor is used at pin VDD.

Table 12: Port B Description

PORT B

I / O

Alternate Function

Input1

1. Reset state.

Output

Signal

Condition

PB0

with Weak Pull-up

when Digital Input

Push-pull

Analog Input

(ADC):AIN0

ADON = 1 & CH[1:0] = 00 (ADCCSR)

PB1

with Weak Pull-up

when Digital Input

Push-pull

Analog Input

(ADC) AIN1

ADON = 1 & CH[1:0] = 01 (ADCCSR)

PB2

with Weak Pull-up

when Digital Input

Push-pull

Analog Input

(ADC) AIN2

ADON = 1 & CH[1:0] = 10 (ADCCSR)

PB3

with Weak Pull-up

when Digital Input

Push-pull

Analog Input

(ADC) AIN3/ IFR

ADON = 1 & CH[1:0] = 11 (ADCCSR) for analog

input. In this case, IFR is disabled.

Figure 19: Port B [2:0]

DR SEL

DDR SEL

Analog

switch

Analog enable

(ADC)

TTL Schmitt Trigger

DDR

latch

VDD

Analog enable

(ADC)

PAD

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