ST7FLCD1_05 datasheet(24/95 Pages) STMICROELECTRONICS

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Interrupts

ST7FLCD1

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Interrupts

There are two different methods to interrupt the ST7:

1. a maskable hardware interrupt as listed in Table 7

2. a non-maskable software interrupt (TRAP).

The Interrupt Processing flowchart is shown in Figure 10.

Only enabled maskable interrupts are serviced. However, disabled interrupts are latched and

processed. For an interrupt to be serviced, the PC, X, A and CC registers are saved onto the stack,

the interrupt mask (bit I of the Condition Code Register) is set to prevent additional interrupts. The

Y register is not automatically saved.

The PC is then loaded with the interrupt vector and the interrupt service routine runs (refer to

Table 7 for vector addresses) and ends with the IRET instruction. At the IRET instruction, the

contents of the registers are recovered from the stack and normal processing resumes. Note that

the I bit is then cleared if the corresponding bit stored in the stack is zero.

Though many interrupts can be run simultaneously, an order of priority is defined (see Table 7). The

RESET pin has the highest priority. If the I bit is set, only the TRAP interrupt is enabled. All

interrupts allow the processor to exit the WAIT Low Power mode.

4.1

Software

The software interrupt is the executable TRAP instruction. The interrupt is recognized when the

TRAP instruction is executed, regardless of the state of the I bit. When an interrupt is recognized, it

is serviced according to flowchart described in Figure 10.

Note:

During ICC communication, the TRAP interrupt is reserved.

4.2

External Interrupts (ITA, ITB)

The ITA (PA6), ITB (PA7) pins generate an interrupt when a falling or rising edge occurs on these

pins. These interrupts are enabled by the ITAITE and ITBITE bits (respectively) in the ITRFRE

interrupt vector.

4.3

Peripheral Interrupts

The various peripheral devices with interrupts include both Display Data Channels (DDC A and

DDC B), the Infrared Controller (IFR), two 8-bit timers (Timer A and Timer B) and the I²C interface.

Different peripheral interrupt flags fetch an interrupt if the I bit from the CC register is reset and the

corresponding Enable bit is set. If any of these conditions is not fulfilled, the interrupt is latched but

not serviced, thus remaining pending.

4.4

Processing

Interrupt flags are located in the status register. The Enable bits are in the control register. When an

enabled interrupt occurs, normal processing is suspended at the end of the current instruction

execution. It is then serviced according to the flowchart shown in Figure 10.

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