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PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 18 of 30
CYP15G0401TB HOTLink II Transmitter Switching Waveforms
Notes:
25. When REFCLK is configured for half-rate operation (TXRATE = HIGH) and data is captured using REFCLK instead of a TXCLKx clock (TXCKSEL = LOW), data
is captured using both the rising and falling edges of REFCLK.
26. The TXCLKO output is at twice the rate of REFCLK when TXRATE = HIGH and same rate as REFCLK when TXRATE = LOW. TXCLKO does not follow the duty
cycle of REFCLK.
27. The rising edge of TXCLKO output has no direct phase relationship to the REFCLK input.
TXCLKx
TXDx[7:0],
TXCTx[1:0],
tTXDH
tTXDS
tTXCLK
tTXCLKH
tTXCLKL
Transmit Interface Write Timing
TXOPx,
SCSEL
TXCKSEL
≠ LOW
REFCLK
Transmit Interface Write Timing
tREFCLK
tREFH
tREFL
tTREFDS
tTREFDH
TXCKSEL = LOW
TXRATE = LOW
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
tTREFDH
Transmit Interface
Write Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
tREFCLK
tREFL
tREFH
Note 25
TXDx[7:0],
TXCTx[1:0],
TXOPx,
SCSEL
tTREFDS
tTREFDS
tTREFDH
Note 25
TXCLKO
tTXCLKO
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = HIGH
REFCLK
tREFCLK
tREFL
tREFH
Note 26
Note 27
tTXCLKOD+
tTXCLKOD–
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