PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 14 of 30
When both the REFCLK+ and REFCLK– inputs are
connected, the clock source must be a differential clock. This
can be either a differential LVPECL clock that is DC- or
AC-coupled, or a differential LVTTL or LVCMOS clock.
By connecting the REFCLK– input to an external voltage
source or resistive voltage divider, it is possible to adjust the
reference point of the REFCLK+ input for alternate logic levels.
When doing so, it is necessary to ensure that the input differ-
ential crossing point remains within the parametric range
supported by the input.
Power Control
The CYP15G0401TB supports user control of the powered up
or down state of each transmit channel. The transmit channels
are controlled by the OELE signal and the values present on
the BOE[7:0] bus. Powering down unused channels will save
power and reduce system heat generation. Controlling system
power dissipation will improve the system performance.
Transmit Channels
When OELE is HIGH, the signals on the BOE[7:0] inputs
directly control the power enables for the Serial Drivers. When
a BOE[x] input is HIGH, the associated Serial Driver is
enabled. When a BOE[x] input is LOW, the associated Serial
Driver is disabled and powered down. If both Serial Drivers of
a channel are disabled, the internal logic for that transmit
channel is powered down. When OELE returns LOW, the
values present on the BOE[7:0] inputs are latched in the
Output Enable Latch.
Device Reset State
When the CYP15G0401TB is reset by assertion of TRSTZ, the
Transmit Enable Latches are cleared, and the BIST Enable
Latch is preset. In this state, all transmit channels are disabled,
and BIST is disabled on all channels.
Following a device reset, it is necessary to enable the transmit
channels used for normal operation. This can be done by
sequencing the appropriate values on the BOE[7:0] inputs
while the OELE signal is raised and lowered. For systems that
do not require dynamic control of power, or want the device to
power up in a fixed configuration, it is also possible to strap the
OELE control signal HIGH to permanently enable its
associated latches. Connection of the associated BOE[7:0]
signals to a stable HIGH will then enable the respective
transmit channels as soon as the TRSTZ signal is deasserted.
JTAG Support
The CYP15G0401TB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, only boundary scan is supported. This capability is
present only on the LVTTL inputs, LVTTL outputs and the
REFCLK
± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
JTAG ID
The JTAG device ID for the CYP15G0401TB is ‘1C800069’x.
Three-level Select Inputs
Each Three-level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11, respectively.
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