FS26 datasheet(117/156 Pages) NXP

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NXP Semiconductors

FS26

Safety system basis chip with low power for ASIL D/ASIL B

GPIO1 configuration

from logic

GPIO1

from logic

to logic

GPIO1

Receiver

QLS

QHS

GPIO1PD

RPD_GPIOx

GPIO1PU

VSUP

TSD

SENSOR

RPU_GPIOx

VDDIO

aaa-045474

VBOS

VDIG

Figure 38. GPIO1 block diagram

GPIO2 configuration

from logic

GPIO2

from logic

to logic

GPIO2

Receiver

QLS

QHS

GPIO2PD

RPD_GPIOx

GPIO2PU

RPU_GPIOx

VDDIO

TRKIN

aaa-045475

VBOS

VDIG

Figure 39. GPIO2 block diagram

19.3.2.1 GPIO input configuration

When GPIOx is set as input configuration, the pin is set to Hi-Z or Low depending on the GPIOxPD_OTP bit.

The internal pull-up is disabled regardless of the GPIOxPD_OTP bit.

GPIOx pins are protected up to 40 V, and are suitable to connect a wake-up signal outside the ECU.

When a GPIO is used as a global input pin, an RC protection network is required to protect the input. When a

GPIO is used as local input pin, a capacitor is required for immunity. Each GPIO voltage can be sensed through

the analog multiplexer.

19.3.2.2 GPIO active high mode

When GPIOx is set as active high, as soon as the OTP is loaded, the pin is set to Hi-Z or Low, depending on the

GPIOxPD_OTP bit. If the GPIOx is assigned to a slot in the power-up sequence, the pin remains Hi-Z or Low

until it reaches the selected slot. Once the selected slot is reached, the GPIOx is asserted high.

In normal mode, the internal pull-down resistor is disabled regardless of the GPIOxPD_OTP bit when the GPIOx

is set as low-side driver.

FS26_SDS

All information provided in this document is subject to legal disclaimers.

Product short data sheet

Rev. 6.0 — 12 December 2025

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