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FS26 Folha de dados(PDF) 49 Page - NXP Semiconductors |
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FS26 Folha de dados(HTML) 49 Page - NXP Semiconductors |
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49 / 156 page  NXP Semiconductors FS26 Safety system basis chip with low power for ASIL D/ASIL B Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Go to main register map Bit Symbol Value Description VBST overvoltage flag. Set when VBST > VBST_OV_TH 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 8 VBSTOV_I Reset on power-on reset (POR_M) or clear on write 1 VPRE undervoltage flag. Set when VPRE_PWM < VPRE_UVH 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 7 VPREUVH_I Reset on power-on reset (POR_M) or clear on write 1 VBST overcurrent event. Set when VBST_ISH pin voltage minus VBST_ISL pin voltage > VBST_ILIM_TH 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 6 VBSTOC_I Reset on power-on reset (POR_M) or clear on write 1 VPRE overcurrent event. Set when IPRE_PWM > IPRE_OC_FLAG 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 5 VPREOC_I Reset on power-on reset (POR_M) or clear on write 1 TRK2 overcurrent event. Set when ITRK2 > ILIM_TRKx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 4 TRK2OC_I Reset on power-on reset (POR_M) or clear on write 1 TRK1 overcurrent event. Set when ITRK1 > ILIM_TRKx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 3 TRK1OC_I Reset on power-on reset (POR_M) or clear on write 1 VCORE overcurrent event. Set when ICORE > ICORE_PEAK_0A8 (for FS260x and FS261x) or ICORE > ICORE_ PEAK_1A65 (for FS262x and FS263x) 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 2 COREOC_I Reset on power-on reset (POR_M) or clear on write 1 LDO2 overcurrent event. Set when ILDO2 > ILIM_LDOx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 1 LDO2OC_I Reset on power-on reset (POR_M) or clear on write 1 LDO1 overcurrent event. Set when ILDO1 > ILIM_LDOx 0h Event not detected 1h Event detected. Generates interrupt (INTB pulse) 0 LDO1OC_I Reset on power-on reset (POR_M) or clear on write 1 Table 27. M_REG_FLG register bit description FS26_SDS All information provided in this document is subject to legal disclaimers. © 2025 NXP B.V. All rights reserved. Product short data sheet Rev. 6.0 — 12 December 2025 Document feedback 49 / 156 |
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