IS61C1024

IS61C1024L

8

SR028-1J

11/03/98

DATA UNDEFINED

LOW

VALID ADDRESS

HIGH-Z

ADDRESS

CE1

WE

OE

HIGH

CE2

CE2_WR2.eps

Notes:

1. The internal write time is defined by the overlap of

CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to

the rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE1

CE2

WE

CE2_WR1.eps

AC WAVEFORMS