IS61C1024

IS61C1024L

4

7

SR028-1K

05/12/99

-15 ns

-20 ns

-25 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

12

—

15

—

20

—

25

—

ns

CE1 to Write End

10

—

12

—

15

—

20

—

ns

CE2 to Write End

10

—

12

—

15

—

20

—

ns

Address Setup Time to Write End

10

—

12

—

15

—

20

—

ns

Address Hold from Write End

0

—

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

0

—

ns

WE Pulse Width

10

—

10

—

12

—

15

—

ns

Data Setup to Write End

7

—

8

—

10

—

12

—

ns

Data Hold from Write End

0

—

0

—

0

—

0

—

ns

WE LOW to High-Z Output

—

7

—

7

—

10

—

12

ns

WE HIGH to Low-Z Output

2

—

2

—

2

—

2

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

3. -12 ns device for IS61C1024 only.

4. Tested with

OE HIGH.

5. Tested with the load in Figure 2. Transition is measured

±500 mV from steady-state voltage. Not 100% tested.