CY8CKIT-059 datasheet(14/140 Pages) INFINEON

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Document Number: 001-84932 Rev. *N

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PSoC® 5LP: CY8C58LP Family

Datasheet

4. CPU

4.1 Arm Cortex-M3 CPU

The CY8C58LP family of devices has an Arm Cortex-M3 CPU core. The Cortex-M3 is a low-power 32-bit three-stage pipelined

Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt

handling features.

Figure 4-1. Arm Cortex-M3 Block Diagram

The Cortex-M3 CPU subsystem includes these features:



Arm Cortex-M3 CPU



Programmable nested vectored interrupt controller (NVIC),

tightly integrated with the CPU core



Full featured debug and trace modules, tightly integrated with

the CPU core



Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB

of SRAM



Cache controller



Peripheral HUB (PHUB)



DMA controller



External memory interface (EMIF)

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:



4 GB address space. Predefined address regions for code,

data, and peripherals. Multiple buses for efficient and

simultaneous accesses of instructions, data, and peripherals.



The Thumb®-2 instruction set, which offers Arm-level

performance at Thumb-level code density. This includes 16-bit

and 32-bit instructions. Advanced instructions include:



Bit-field control



Hardware multiply and divide



Saturation



If-Then



Wait for events and interrupts



Exclusive access and barrier



Special register access

Nested

Vectored

Interrupt

Controller

(NVIC)

Debug Block

(Serial and

JTAG)

Embedded

Trace Module

(ETM)

Trace Port

Interface Unit

(TPIU)

Interrupt Inputs

JTAG/SWD

Trace Pins:

5 for TRACEPORT or

1 for SWV mode

Cortex M3 CPU Core

I- Bus

S-Bus

D-Bus

256 KB

ECC

Flash

1 KB

Cache

32 KB

SRAM

DMA

AHB Bridge & Bus Matrix

PHUB

GPIO &

EMIF

Prog.

Digital

Prog.

Analog

Special

Functions

Peripherals

AHB Spokes

AHB

Bus

Matrix

Cortex M3 Wrapper

C-Bus

Data

Watchpoint and

Trace (DWT)

Instrumentation

Trace Module

(ITM)

Flash Patch

and Breakpoint

(FPB)

Bus

Matrix

32 KB

SRAM

Bus

Matrix

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