UCD3138A64 datasheet(41/84 Pages) TI2

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UCD3138128, UCD3138A64

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SLUSBZ8B – JUNE 2014 – REVISED FEBRUARY 2017

Product Folder Links: UCD3138128 UCD3138A64

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The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be set

either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is stored in the

corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which are the counter

rollover event (overflow), capture events 0 and 1, and the two comparison match events. Each interrupt can be

disabled or enabled.

9.3.8.2 16-Bit PWM Timers

There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a

8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for

generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register)

which can be used to store CPU updates of compare events while still using the timer. The selected shadow

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software

controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by

the two comparison match events. Each comparison match and the overflow interrupts can be disabled or

enabled.

Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output.

The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the

value of the input at the pin.

9.3.8.3 Watchdog Timer

A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off

of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM

processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine.

On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by

firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided

for status monitoring of the watchdog.

9.3.9 General Purpose ADC12

The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:

•

Typical conversion speed of 267 ksps

•

Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence

•

Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples

•

Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,

ADC_EXT_TRIG pin or Analog Comparator results

•

Interrupt capability to embedded processor at completion of ADC conversion

•

Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or

averaged ADC data

•

Two 10 µA current sources for excitation of PMBus addressing resistors

•

Dual sample and hold for accurate power measurement

•

Internal temperature sensor for temperature protection and monitoring

The control module (ADC12 Contol Block Diagram) contains the control and conversion logic for auto-

sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC

channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel

value is stored in the result register associated with the sequence number. Input channels can be sampled in any

desired order or programmed to repeat conversions on the same channel multiple times during a conversion

sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the

result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a

16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16.

Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the

ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster

conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best

suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical

Characteristics plots for the temperature variation associated with this function.

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