UCD3138RMHR datasheet(26/99 Pages) TI2

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9 Detailed Description

9.1 Overview

The UCD3138 family is a digital power supply controller from Texas Instruments offering superior levels of

integration and performance in a single chip solution. The UCD3138x, in comparison to Texas Instruments

UCD3138 digital power controller offers 32 kB of program Flash memory. The flexible nature of the UCD3138

family makes it suitable for a wide variety of power conversion applications.

In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance

of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network

infrastructure space. The UCD3138 family is a fully programmable solution offering customers complete control

of their application, along with ample ability to differentiate their solution. At the same time, TI is committed

to simplifying our customer’s development effort through offering best in class development tools, including

application firmware, Code Composer StudioTM software development environment, and TI’s Fusion Power

Development GUI which enables customers to configure and monitor key system parameters.

9.2 ARM Processor

The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit

microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where

two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The

Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the performance of

the 32-bit microprocessor.

The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in

the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.

9.3 Memory

The UCD3138 (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the

memory modules. All of the memory module addresses are sequentially aligned along the same address range.

This applies to program flash, data flash, ROM and all other peripherals.

Within the UCD3138 architecture, there is a Boot ROM that contains the initial firmware startup routines for

PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-

up-reset checks if there is a valid FLASH program written. If a valid program is present, the ROM code branches

to the main FLASH-program execution.

UCD3138 also supports customization of the boot program by allowing an alternative boot routine to be

executed from program FLASH. This feature enables assignment of a unique address to each device; therefore,

enabling firmware reprogramming even when several devices are connected on the same communication bus.

Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is organized as

an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is configured with page

erase capability for erasing blocks as small as 1kB per page, or with a mass erase for erasing the entire program

FLASH array. The FLASH endurance is specified at 1000 erase/write cycles and the data retention is good for

100 years. The 2 kB data FLASH array is organized as a 512 x 32 bit memory (32 byte page size). The Data

FLASH is intended for firmware data value storage and data logging. Thus, the Data FLASH is specified as a

high endurance memory of 20 k cycles with embedded error correction code (ECC).

For run time data storage and scratchpad memory, a 4 kB RAM is available. The RAM is organized as a 1 k x 32

bit array.

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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