UCD3138RJAR datasheet(29/99 Pages) TI2

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9.4.3 System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or

peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or

access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.

9.4.4 Central Interrupt Module (CIM)

The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports

two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of

interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index

value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector

address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31

has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first

action in the interrupt service routine. The request channels are maskable, allowing individual channels to be

selectively disabled or enabled.

Table 9-4. Interrupt Priority Table

NAME

MODULE COMPONENT OR

DESCRIPTION

PRIORITY

BRN_OUT_INT

Brownout

Brownout interrupt

0 (lowest)

EXT_INT

External interrupts

Interrupt on external input pin

WDRST_INT

Watchdog control

Interrupt from watchdog exceeded (reset)

WDWAKE_INT

Watchdog control

Wakeup interrupt when watchdog equals half of set

watch time

SCI_ERR_INT

UART or SCI control

UART or SCI error Interrupt. Frame, parity or overrun

SCI_RX_0_INT

UART or SCI control

UART0 RX buffer has a byte

SCI_TX_0_INT

UART or SCI control

UART0 TX buffer empty

SCI_RX_1_INT

UART or SCI control

UART1 RX buffer has a byte

SCI_TX_1_INT

UART or SCI control

UART1 TX buffer empty

PMBUS_INT

PMBus related interrupt

DIG_COMP_INT

12-bit ADC control

Digital comparator interrupt

FE0_INT

Front End 0

“Prebias complete”, “Ramp Delay Complete”, “Ramp

Complete”, “Load Step Detected”,

“Over-Voltage Detected”, “EADC saturated”

FE1_INT

Front End 1

“Prebias complete”, “Ramp Delay Complete”, “Ramp

Complete”, “Load Step Detected”,

“Over-Voltage Detected”, “EADC saturated”

FE2_INT

Front End 2

“Prebias complete”, “Ramp Delay Complete”, “Ramp

Complete”, “Load Step Detected”,

“Over-Voltage Detected”, “EADC saturated”

PWM3_INT

16-bit timer PWM 3

16-bit Timer PWM3 counter overflow or compare interrupt

PWM2_INT

16-bit timer PWM 2

16-bit Timer PWM2 counter Overflow or compare

interrupt

PWM1_INT

16-bit timer PWM 1

16-bit Timer PWM1 counter overflow or compare interrupt

PWM0_INT

16-bit timer PWM 0

16-bit Timer PWM1 counter overflow or compare interrupt

OVF24_INT

24-bit timer control

24-bit Timer counter overflow interrupt

CAPTURE_1_INT

24-bit timer control

24-bit Timer capture 1 interrupt

COMP_1_INT

24-bit timer control

24-bit Timer compare 1 interrupt

CAPTURE_0_INT

24-bit timer control

24-bit Timer capture 0 interrupt

COMP_0_INT

24-bit timer control

24-bit Timer compare 0 interrupt

CPCC_INT

Constant power constant current

Mode switched in CPCC module Flag needs to be read

for details

ADC_CONV_INT

12-bit ADC control

ADC end of conversion interrupt

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UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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