UCD3138RJAR datasheet(17/99 Pages) TI2

17 / 99 page

8.5 Electrical Characteristics (continued)

V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VTEMP

Voltage range of sensor

1.46

2.44

Voltage resolution

V/°C

5.9

mV/°C

Temperature resolution

°C per bit

0.1034

°C/LSB

Accuracy(6) (7)

–40°C to 125°C

–10

±5

°C

Temperature range

–40°C to 125°C

–40

125

°C

ITEMP

Current draw of sensor when active

μA

TON

Turn on time / settling time of sensor

100

μs

VAMB

Ambient temperature

Trimmed 25°C reading

1.85

ANALOG COMPARATOR

DAC

Reference DAC Range

2.5

Reference Voltage

2.478

2.5

2.513

Bits

bits

INL(6)

–0.42

0.21

LSB

DNL(6)

0.06

0.12

LSB

Offset

–5.5

19.5

Time to disable DPWM output based on

0 V to 2.5 V step input on the analog

comparator.(1)

150

Reference DAC buffered output load(8)

0.5

Buffer offset (–0.5 mA)

4.6

8.3

Buffer offset (1.0 mA)

–0.05

(1)

As designed and characterized. Not 100% tested in production.

(2)

DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(3)

On the 40-pin package V33DIO is connected to V33D internally.

(4)

The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage

drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.

(5)

Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which

has no variation associated with it, must be accounted for when calculating the system dynamic response.

(6)

Characterized by design and not production tested.

(7)

Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.

(8)

Available from reference DACs for comparators D, E, F, and G.

8.6 Timing and Switching Characteristics

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and

PMBus in Slave or Master mode are shown in PMBus/SMBus/I2C Timing, I2C/SMBus/PMBus Timing Diagram,

and Bus Timing in Extended Mode. The numbers in PMBus/SMBus/I2C Timing arµe for 400 kHz operating

frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz), and fast mode

plus (1 MHz).

Table 8-1. PMBus/SMBus/I2C Timing

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)

fSMB

SMBus/PMBus operating frequency

Slave mode, SMBC 50% duty cycle

100 1000

kHz

fI2C

I2C operating frequency

Slave mode, SCL 50% duty cycle

100 1000

kHz

t(BUF)

Bus free time between start and stop

1.3

µs

t(HD:STA)

Hold time after (repeated) start(1)

0.6

µs

t(SU:STA)

Repeated start setup time(1)

0.6

µs

t(SU:STO)

Stop setup time(1)

0.6

µs

t(HD:DAT)

Data hold time

Receive mode

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UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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