UCD3138RGCT.A datasheet(44/99 Pages) TI2

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ADC

Channels

S/H

12-bit SAR

ADC

12-bit SAR

ADC

ADC12 Block

ADC12

Control

ADC Channel

ADC

Averaging

Digital

Comparators

DPWM

Modules

ADC12 Registers

Analog

Comparators

ADC External Trigger (from pin)

Figure 9-14. ADC12 Control Block Diagram

9.5.5.4 Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138. They are the 24-bit

timer, 16-bit timer and the Watchdog timer

9.5.5.4.1 24-bit PWM Timer

There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down by

an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data Registers)

for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data Buffer register)

which can be used to store CPU updates of the compare events while still using the timer. The selected shadow

The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can be

set either to rising, falling, or both edges of the capture pin. Upon this event, the counter value is stored in the

corresponding capture data register.

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by software

controlled register. Five Interrupts from the PWM timer can be set, which are the counter rollover event

(overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt can be disabled

or enabled.

Upon an event comparison on only the second event, the TCMP pin can be configured to set, clear, toggle

or have no action at the output. The value of PWM pin output can be read for status or simply configured as

general purpose I/O for reading the value of the input at the pin. The first compare event can only be used as an

interrupt.

9.5.5.4.2 16-Bit PWM Timers

There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by

a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers)

for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register)

which can be used to store CPU updates of compare events while still using the timer. The selected shadow

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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