UCD3138RGCT.A datasheet(30/99 Pages) TI2

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Table 9-4. Interrupt Priority Table (continued)

NAME

MODULE COMPONENT OR

DESCRIPTION

PRIORITY

FAULT_INT

Fault Mux interrupt

Analog comparator interrupts, overvoltage detection,

undervoltage detection, LLM load step detection

DPWM3

Same as DPWM1

DPWM2

Same as DPWM1

DPWM1

1) Every (1 to 256) switching cycles

2) Fault detection

3) Mode switching

DPWM0

Same as DPWM1

EXT_FAULT_INT

External Faults

Fault pin interrupt

SYS_SSI_INT

System Software

System software interrupt

31 (highest)

9.5 Feature Description

9.5.1 Sync FET Ramp and IDE Calculation

The UCD3138 has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This comes

in two forms:

• Sync FET ramp

• Ideal Diode Emulation (IDE) calculation

When starting up a power supply, sometimes there is already a voltage on the output – this is called prebias. It is

very difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated correctly, it may pull down

the prebias voltage, causing the power supply to sink current.

To avoid this, Sync FETs are not turned on until after the power supply has ramped up to the nominal voltage.

The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET Ramp logic can

be used to turn them on at a rate below the bandwidth of the filter.

In discontinuous mode, the ideal on-time for the Sync FETs is a function of Vin, Vout, and the primary side duty

cycle (D). The IDE logic in the UCD3138 takes Vin and Vout data from the firmware and combines it with D data

from the filter hardware. It uses this information to calculate the ideal on-time for the Sync FETs.

9.5.2 Automatic Mode Switching

Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware

intervention. This is useful to increase efficiency and power range. The following paragraphs describe phase-

shifted full bridge and LLC examples:

9.5.2.1 Phase Shifted Full Bridge Example

In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather than

phase shift, at light load. This is shown below:

UCD3138

SLUSAP2J – MARCH 2012 – REVISED NOVEMBER 2021

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