DALC208SC6 datasheet(5/10 Pages) STMICROELECTRONICS

5 / 10 page

HOW TO ENSURE A GOOD ESD PROTECTION

While the DALC208SC6 provides a high immunity

to ESD surge, an efficient protection depends on

the layout of the board. In the same way, with the

rail to rail topology, the track from the VREF2 pin to

the power supply +VCC and from the VREF1 pin to

GND must be as short as possible to avoid

overvoltages due to parasitic phenomena (see Fig.

A1).

It’s often harder to connect the power supply near

to the DALC208SC6 unlike the ground thanks to

the ground plane that allows a short connection.

To ensure the same efficiency for positive surges

when the connections can’t be short enough, we

recommend to put close to the DALC208SC6,

between VREF2 and ground, a capacitance of

100nF to prevent from these kinds of overvoltage

disturbances (see Fig. A2).

The add of this capacitance will allow a better

protection by providing during surge a constant

voltage.

Fig. A3, A4a and A4b show the improvement of the

ESD protection according to the recommendations

described above.

REF1=GND

VI/O

ESD

SURGE

I/O

REF2=+Vcc

C=100nF

Vcl+ = Vcc+Vf

-Vf

surge >0

surge <0

Vcl- =

Vcl+

POSITIVE

SURGE

Vcl-

NEGATIVE

SURGE

Fig. A2: ESD behavior: optimized layout and add

of a capacitance of 100nF.

Important:

A main precaution to take is to put the protection

device closer to the disturbance source (generally

the connector).

+5V

TEST BOARD

DALC

208

ESD

SURGE

Fig. A3: ESD behavior: measurements conditions

(with coupling capacitance).

IEC 1000-4-2

Air Discharge

(150pF/330

Ω)

Vpp=15kV

Fig. A4a: Remaining voltage after the

DALC208SC6 during positive ESD surge.

IEC 1000-4-2

Air Discharge

(150pF/330

Ω)

Vpp=15kV

Fig. A4b: Remaining voltage after the

DALC208SC6 during negative ESD surge.

Note: The measurements have been done with the DALC208SC6

in open circuit.

DALC208SC6

5/10

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