STPM098C datasheet(27/110 Pages) STMICROELECTRONICS

27 / 110 page

3.4.2.1

Latched faults

When a latched fault is detected, the related PMBus™ flag is set to ‘1’ and related fault redirection pins are

asserted low. Internal logic reacts by establishing a SAFE_HIZ state: PWM outputs go in HIZ mode so that PWMn

= HIZ [n = 1, 2, 3, 4, 5, 6, 7, 8].

The SAFE_HIZ mode can be left when all the following conditions are met in this sequence:

1. Latched fault is removed.

2. Clear mechanism - One of the following actions, required by application software:

–

VR_EN1/VR_EN2 is asserted low for at least T_clear and then asserted back high.

–

CLEAR_FAULTS command by PMBus™ (clears all faults).

–

Dedicated clear commands by PMBus™ (clears single fault).

Note:

•

VR1_EN toggling is used to clear specific fault affecting loop 1. VR2_EN toggling is used to clear specific

fault affecting loop 2. Generic faults affecting both loops can be cleared by toggling either VR1_EN or

VR2_EN.

•

Faults clearing through the PMBus™ command make use of paging for faults affecting the specific loop.

Generic faults affecting both loops can be cleared independently of the command page.

Figure 15. Latched fault - Transient fault timing diagram

DRIVE

Fault

Occurrence

FAULT

(PMBus

Flag)

FAULT (pin)

VRRDY (pin)

SM_ALERT

(pin)

VRn_EN

PWMn

Fault disappear

Fault appear

Tclear (**)

3Tclk

HiZ

(*)

(*) Signaling Filter Time = Fault Detection + Reaction Time

(**) Tclear is the minimum time VRn_EN shall be asserted LOW for fault clear to be effective

Fault Detection +

Reaction Time

STPM098C

Functional description

DS14440 - Rev 1

page 27/110

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