MB85RS4MTY(AEC-Q100 Compliant)

14

DS501-00066-3v0-E



FSSRD

The SSRD command reads data from special sector (a special region of 256 Byte in FeRAM). SSWR op-

code and arbitrary 24 bits address are input to SI followed by 8 bits dummy. The 16-bit upper address is

invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While

reading, the SI value is invalid. When CS is risen, the SSRD command is completed, but keeps on reading

with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles

before CS rising. When it reaches the most significant address, roll over is not happen.

The data in special sector is stable between before and after reflow. Refer “ REFLOW CONDITIONS AND

FLOOR LIFE” for the reflow condition.



DPD(Deep Power Down)

The DPD command shifts the LSI to a low power mode called “DPD mode”. The transition to the DPD mode

is carried out at the rising edge of CS after operation code in the DPD command. However, when at least

one SCK clock is inputted before the rising edge of CS after operation code in the DPD command, this DPD

command is canceled.

After the DPD mode transition, SCK and SI inputs are ignored and SO changes to a High-Z state.

Returning to an normal operation from the DPD mode is carried out after tRECDPD (Max 10 s) time from the

falling edge of CS (see the figure below). It is possible to return CS to H level before tRECDPD time. However,

it is prohibited to bring down CS to L level again during tRECDPD period.

CS

SCK

SI

Invalid

MSB

LSB

MSB

Data Out

LSB

High-Z

Invalid

45

0123

29 30

6

8 9 1011

25262728

4647

31 32

38 39 40 41 42 43 44 45

01001001 X

6

4

210 X

XX

SO

7

XXX

65

0

543

33

X

21

3

24

23

7

X

7

24 bit addresses

ope. code

8 bit dummy

Enter DPD Mode

CS

SCK

SI Invalid

Invalid

High-Z

DPD Mode Entry

67

012345

SO

0

1011101

CS

CS

tRECDPD

Exit DPD Mode

DPD Mode Exit

tCSWL

From this time

Command input enable