Figure 42. EMIRR on In+ and In- pins

EMIRR performances might be improved by adding small capacitances (in the pF range) on the inputs, power

supply and output pins. These capacitances help minimize the impedance of these nodes at high frequencies.

5.6

Maximum power dissipation

The usable output load current drive is limited by the maximum power dissipation allowed by the device package.

The absolute maximum junction temperature for the TSV78x is 150 °C. The junction temperature can be

estimated as follows:

TJ=PD×θJA+TA

(10)

TJ is the die junction temperature

PD is the power dissipated in the package

θJA is the junction to ambient thermal resistance of the package.

TA is the ambient temperature.

The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated

by the output stage transistor. It is calculated as follows:

PD= VCC×ICC + VCC+−VOUT ×ILoadwhentheopampissourcingthecurrent.

PD= VCC×ICC + VOUT−VCC− ×ILoadwhentheopampissinkingthecurrent.

Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit

can cause degradation in the parametric performance or even destroy the device.

5.7

Capacitive load and stability

A stability analysis must be performed for large capacitive loads over 22 pF. Increasing the load capacitance to

high values produces gain peaking in the frequency response, with overshoot and ringing in the step response.

Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.

For additional capacitive load drive capability in unity-gain configurations, stability can be improved by inserting a

small resistor RISO (10 Ω to 22 Ω) in series with the output. This resistor significantly reduces ringing while

maintaining DC performance for purely capacitive loads. However, if there is a resistive load in parallel with the

capacitive load, a voltage divider is created introducing a gain error at the output and slightly reducing the output

swing. The error introduced is proportional to the ratio RISO / RL. RISO modifies the maximum capacitive load

acceptable from a stability point-of-view as described in the figure below:

TSV781, TSV782

Application information

DS14011 - Rev 7

page 20/34