TSC2014IYZGR datasheet(43/62 Pages) TI2

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TSC2014

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SBAS484B – SEPTEMBER 2010 – REVISED DECEMBER 2016

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7.6.4.1.3

Resolution control. The A/D converter resolution is specified with this bit. See Table 13 for a description of these

bits. This bit is the same whether reading or writing, and defaults to 0. Note that the same bit can be written

through Control Byte 1.

Table 13. A/D Converter Resolution Control

FUNCTION

10-bit resolution. Power-up and reset default.

12-bit resolution

(1)

For VDD = 1.2V at –40°C, a lower A/D converter clock rate should be used to allow enough time for conversion settling.

7.6.4.1.4

CL1, CL0

Conversion clock control. These two bits specify the clock rate that the A/D converter uses to perform

conversion, as shown in Table 14.

Table 14. A/D Converter Conversion Clock Control

CL1

CL0

FUNCTION

fADC = fOSC/1. This is referred to as the 4MHz A/D converter clock rate, 10-bit resolution only

(1).

fADC = fOSC/2. This is referred to as the 2MHz A/D converter clock rate.

fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate.

7.6.4.1.5

PV2-PV0

Panel voltage stabilization time control. These bits specify a delay time from the moment the touch screen drivers

are enabled to the time the voltage is sampled and a conversion is started. These bits allow the user to adjust

the appropriate settling time for the touch panel and external capacitances. See Table 15 for settings of these

bits. The default state is 000, indicating a 0μs stabilization time. These bits are the same whether reading or

writing.

Table 15. Panel Voltage Stabilization Time Control

PV2

PV1

PV0

STABILIZATION TIME (tPVS)

0μs

100μs

500μs

1ms

5ms

10ms

50ms

100ms

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