LPC2917 datasheet(13/68 Pages) PHILIPS

13 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

13 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

7.2.2 Base clock and branch clock relationship

The next table contains an overview of all the base blocks in the LPC2917/19 and their

derived branch clocks. A short description is given of the hardware parts that are clocked

with the individual branch clocks. In relevant cases more detailed information can be

found in the specific subsystem description. Some branch clocks have special protection

since they clock vital system parts of the device and should (for example) not be switched

off. See Section 8.8.6 for more details of how to control the individual branch clocks.

Table 7.

Base clock and branch clock overview

Base clock

Branch clock name

Parts of the device clocked by

this branch clock

Remark

BASE_SAFE_CLK

CLK_SAFE

Watchdog Timer

[1]

BASE_SYS_CLK

CLK_SYS_CPU

ARM968E-S and TCMs

CLK_SYS_SYS

AHB Bus infrastructure

CLK_SYS_PCRSS

AHB side of bridge in PCRSS

CLK_SYS_FMC

Flash-Memory Controller

CLK_SYS_RAM0

Embedded SRAM Controller 0

(32 KByte)

CLK_SYS_RAM1

Embedded SRAM Controller 1

(16 KByte)

CLK_SYS_SMC

External Static-Memory

Controller

CLK_SYS_GESS

General Subsystem

CLK_SYS_VIC

Vectored Interrupt Controller

CLK_SYS_PESS

Peripheral Subsystem

[2] [4]

CLK_SYS_GPIO0

GPIO bank 0

CLK_SYS_GPIO1

GPIO bank 1

CLK_SYS_GPIO2

GPIO bank 2

CLK_SYS_GPIO3

GPIO bank 3

CLK_SYS_IVNSS_A

AHB side of bridge of IVNSS

BASE_PCR_CLK

CLK_PCR_SLOW

PCRSS, CGU, RGU and PMU

logic clock

[1], [3]

BASE_IVNSS_CLK

CLK_IVNSS_VPB

VPB side of the IVNSS

CLK_IVNSS_CANCA

CAN controller Acceptance Filter

CLK_IVNSS_CANC0

CAN channel 0

CLK_IVNSS_CANC1

CAN channel 1

CLK_IVNSS_LIN0

LIN channel 0

CLK_IVNSS_LIN1

LIN channel 1

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