MPC8358E datasheet(13/96 Pages) FREESCALE

13 / 96 page

MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

Clock Input Timing

Table 5 shows the estimated typical I/O power dissipation for the device.

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8358E.

4.1

DC Electrical Characteristics

Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.

Table 5. Estimated Typical I/O Power Dissipation

Interface

Parameter

GVDD

(1.8 V)

GVDD

(2.5 V)

OVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V)

Unit

Comments

DDR I/O

65% utilization

2.5 V

Rs = 20 Ω

Rt = 50 Ω

2 pairs of

clocks

200 MHz, 1x32 bits

0.3

0.46

200 MHz, 1x64 bits

0.4

0.58

200 MHz, 2x32 bits

0.6

0.92

266 MHz, 1x32 bits

0.35

0.56

266 MHz, 1x64 bits

0.46

0.7

266 MHz, 2x32 bits

0.7

1.11

Local Bus I/O

Load = 25 pf

3 pairs of

clocks

133 MHz, 32 bits

0.22

83 MHz, 32 bits

0.14

66 MHz, 32 bits

0.12

50 MHz, 32 bits

0.09

PCI I/O

Load = 30 pf

33 MHz, 32 bits

0.05

66 MHz, 32 bits

0.07

10/100/1000

Ethernet I/O

Load = 20 pf

MII or RMII

0.01

Multiply by number

of interfaces used.

GMII or TBI

0.04

RGMII or RTBI

0.04

Other I/O

0.1

Table 6. CLKIN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

OVDD + 0.3

Input low voltage

—

VIL

–0.3

0.4

CLKIN input current

0 V

≤ VIN ≤ OVDD

IIN

—±10

μA

PCI_SYNC_IN input current

0 V

≤ VIN ≤ 0.5V or

OVDD – 0.5V ≤ VIN ≤ OVDD

IIN

—±10

μA

PCI_SYNC_IN input current

0.5 V

≤ VIN ≤ OVDD – 0.5 V

IIN

—±100

μA

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