MPC8358E datasheet(83/96 Pages) FREESCALE

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MPC8358E PowerQUICC™ II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 1

Freescale Semiconductor

Clocking

NOTE

The VCO divider (RCWL[CEVCOD]) must be set properly so that the QE

VCO frequency is in the range of 600–1400 MHz. The QE frequency is not

restricted by the CSB and core frequencies. The CSB, core, and QE

frequencies should be selected according to the performance requirements.

The QE VCO frequency is derived from the following equations:

ce_clk = (primary clock input × CEPMF)

÷ (1 + CEPDF)

QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)

22.4

Suggested PLL Configurations

To simplify the PLL configurations, the device might be separated into two clock domains. The first

domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and

has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock

domains are independent, and each of their PLLs are configured separately. Both of the domains has one

common input clock. Table 74 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks

and illustrates each of the clock domains separately. Any combination of clock domains setting with same

input clock are valid. Refer to Section 22, “Clocking,” for the appropriate operating frequencies for your

device.

Table 74. Suggested PLL Configurations

Conf

No. 1

SPMF

CORE

PLL

CEPMF

CEPDF

Input

Clock Freq

(MHz)

CSB Freq

(MHz)

Core Freq

(MHz)

QUICC

Engine

Freq (MHz)

400

(MHz)

533

(MHz)

667

(MHz)

33 MHz CLKIN / PCI_SYNC_IN Options

0100

0000100

133

266

∞∞

∞

0100

0000101

133

333

∞∞

∞

0101

0000100

166

333

∞∞

∞

0101

0000101

166

416

∞∞

0110

0000100

200

400

∞∞

∞

0110

0000110

200

600

∞

0111

0000011

233

350

∞∞

∞

0111

0000100

233

466

∞∞

0111

0000101

233

583

∞

s10

1000

0000011

266

400

∞∞

∞

s11

1000

0000100

266

533

∞∞

s12

1000

0000101

266

667

∞

s13

1001

0000010

300

∞∞

∞

s14

1001

0000011

300

450

∞∞

s15

1001

0000100

300

600

∞

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