ADA4352-2ACPZ-R7 datasheet(44/47 Pages) AD

44 / 47 page

Data Sheet

ADA4352-2

analog.com

Rev 0

44 of 47

To minimize picking up stray high frequency signals on the same board, other signal traces must be routed well

away from the TIA’s signal path, and there must be no internal power planes under the high impedance node. The

best defense from coupling signals is shielding; however, this increases capacitance in the area, which impacts the

noise gain of the PGTIA. Another method to decouple signals is distance, which includes vertical layers of the PCB

as well as on the surface of the PCB. The package of the ADA4352-2 simplifies board layout because there is no

exposed pad (EPAD) on the back side of the package, eliminating the need for vias and allowing routing on all

layers of the PCB beneath the device.

In cases where the space is limited, it is recommended to cut slots in the PCB around the high impedance input

nodes to provide additional isolation and to reduce the impact of contamination on the surface of the PCB.

Figure 85. Example PCB Layout for Low Surface Leakage

Board Space Saving Compared to Equivalent Discrete Solution

Due to its integrated switches and resistors, ADA4352-2 uses 8.6% of the board area of a similar discrete solution

with separate resistors and switches. In the layout comparison in Figure 86, ADA4352-2 provides 4 gain settings per

channel, while the other two solutions only provide 2 per channel.

–IN A

+IN A

+IN B

–IN B

SW SEL0 A

SW SEL1 A

SW SEL1 B

SW SEL0 B

ADA4352-2

TOP VIEW

(Not to Scale)

VBIAS

PHOTODIODE

CHANNEL A

PHOTODIODE

CHANNEL B

VBIAS

VCM

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