ADA4352-2ACPZ-R7 datasheet(30/47 Pages) AD

30 / 47 page

Data Sheet

ADA4352-2

analog.com

Rev 0

30 of 47

For RSH >> RFX, noise gain reduces to 1.

Because the offset is a voltage error, it impacts the usable and accurate codes of the ADC for all TIA gains in a

similar way. The ADA4352-2 uses proprietary in-package offset and offset-drift trim to minimize this error.

Input Bias Current

In a PGTIA, the noninverting input bias current (IB+) adds to the total output DC error when the +IN source resistance

(RIN+) is large. For example, 1 nA of input bias current at the noninverting input adds 1 mV of offset for 1 MΩ of

source resistance. Similarly, input bias current at the inverting input (IB-) is only significant at the highest gain

setting, as it is multiplied by the gain resistance. These input bias currents increase exponentially with junction

temperature (TJ). Typically, for an amplifier with CMOS input devices, the input bias current is dominated by

leakage through the electrostatic discharge (ESD) protection diodes. The ADA4352-2 is designed with proprietary

architecture to reduce the reverse-biased leakage of these ESD protection diodes on the all sensitive pins.

Switch Off Leakage Current

Only one of the gain-setting integrated switches can be on at any time. Leakage currents from each of the other

three open switches (IOFF) and the inverting input bias current (IB-) sum back into the active channel (see Figure 69).

Both IOFF and IB− increase exponentially with temperature. For a CMOS switch, there is a trade-off between on-

resistance (RON) and IOFF. Another important aspect of CMOS switches is that IOFF increases when operating the

switch near the supply rail. Not only does ADA4352-2 have low IOFF switches, but also the low leakage performance

extends to 0.1 V from the rail, resulting in a wider usable range for the TIA circuit.

Figure 69. Leakage Current Contributions to Output Voltage Error in the ADA4352-2

Output-Referred Offset Voltage

The output-referred offset voltage is the sum of errors due to the input bias current of the inverting input (IB-),

switch off leakage current (IOFF), and input offset voltage. The ADA4352-2 achieves a maximum of 130 µV output

offset voltage at 25°C with the lowest selectable gain and 1.1 µV/°C drift from −40°C to +125°C at a 5 V supply.

For example, a 16-bit ADC with a 4.5 V reference has a 68.7 µV step size.

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where, N is the ADC resolution.

ADA4352-2

GAIN RESISTOR NETWORK

OUT

RF2 = 40.2kΩ

IOFF3

IOFF2

IOFF1

IIN

RF3 = 450kΩ

VOUT = (IIN + IB + IOFF1 + IOFF2 + IOFF3) × RF0

RF0 = 315Ω

RF1 = 3.5kΩ

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