ST10F272M datasheet(77/175 Pages) STMICROELECTRONICS

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ST10F272M

System reset

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System reset

System reset initializes the MCU in a predefined state. There are six ways to activate a reset

state. The system start-up configuration is different for each case as shown in Table 41.

The figures in the upcoming sections 20.2, 20.3, 20.5 and 20.6 use the following

terminology:

●

transparent

= level of the pin affects the internal reset logic

●

not transparent = level of the pin does not affect internal logic

20.1

Input filter

On the RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all spikes

shorter than 50ns. On the other hand, a valid pulse longer than 500ns is required for the

ST10 to recognize a reset command. In between 50ns and 500ns a pulse can either be

filtered or recognized as valid, depending on the operating conditions and process

variations.

For this reason all minimum durations mentioned in this chapter for the different kinds of

reset events must be carefully evaluated, taking into account the above requirements.

In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input

reset pulse duration, the operating frequency is a key factor.

Examples:

●

For a CPU clock of 40 MHz, 4 TCL is 50ns, so it would be filtered. In this case the

minimum becomes the one imposed by the filter (that is 500ns).

●

For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula

is coherent with the limit imposed by the filter.

Table 41.

Reset event definition

Reset source

Flag

RPD

status

Conditions

Power-on reset

PONR

Low

Power-on

Asynchronous Hardware

reset

LHWR

Low

tRSTIN >

(1)

RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.

Synchronous Long Hardware

reset

High

tRSTIN > (1032 + 12) TCL + max(4 TCL, 500ns)

(2)

See next Section 20.1 for more details on minimum reset pulse duration.

Synchronous Short Hardware

reset

SHWR

High

tRSTIN > max(4 TCL, 500ns)

(2)

tRSTIN < (1032 + 12) TCL + max(4 TCL, 500ns)

(2)

Watchdog Timer reset

WDTR

(3)

The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD

low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to

Sections 20.4, 20.5 and 20.6).

WDT overflow

Software reset

SWR

(3)

SRST instruction execution

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