ADIN1111BCPZ-R7 datasheet(59/109 Pages) AD

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Data Sheet

ADIN1111

REGISTERS

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Rev. A | 59 of 109

Table 68. Bit Descriptions for MAC_RST_STATUS

Bits

Bit Name

Description

Reset

Access

[31:2]

RESERVED

Reserved.

0x0

MAC_CRYSL_CLK_RDY

MAC Crystal Clock Ready. If 0, this field indicates that the MAC core has not been released

from reset. If 1, this field indicates that the MAC core is released from reset. The MAC core is

released from reset when the crystal clock (25 MHz) is ready.

0x1

MAC_OSC_CLK_RDY

MAC Oscillator Clock Ready.

0x1

Software Reset Register

Address: 0x3C, Reset: 0x00000000, Name: SOFT_RST

Table 69. Bit Descriptions for SOFT_RST

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:0]

RST_KEY

Software Reset. Write a pair of keys in order and back to back on the SPI to trigger a reset.

0x0

0x4F1C: Key 1 to reset the MAC logic only.

0xC1F4: Key 2 to reset the MAC logic only. Reset does not take effect until CS is brought high, and CS must

be held asserted for at least 100 ns for the reset to take effect. If the MAC-PHY is in software power-down

mode, the MAC_ONLY reset has no effect. That is, CRSM_SFT_P_CNTRL.CRSM_SFT_PD must be 0.

0x6F1A: Key 1 to request release of reset to the MAC core logic. Use MAC_RST_EXIT_REQ_KEYx to

request a release of reset to the MAC core logic when the 25 MHz crystal clock is not available. This brings

the MAC out of reset using the oscillator clock (12.5 MHz to 25.7 MHz). SPI accesses can then proceed at 15

MHz to allow debug access to MAC and PHY registers.

0xA1F6: Key 2 to request release of reset to the MAC core logic.

Inject an Error on MISO from the DUT Register

Address: 0x3D, Reset: 0x00000000, Name: SPI_INJ_ERR

Table 70. Bit Descriptions for SPI_INJ_ERR

Bits

Bit Name

Description

Reset

Access

[31:1]

RESERVED

Reserved.

0x0

TEST_SPI_INJ_ERR

Inject an Error on the SPI MISO Path. This function allows software to test that errors received on

MISO are properly detected in software. If set and using the OPEN Alliance SPI protocol for data

transaction, the parity bit in the Rx footer is inverted. Also, the time stamp parity bit in the in Rx

footer is inverted. If set and using the OPEN Alliance SPI protocol for protected control burst write

transactions, starting from the second word in a burst, the MS bit of each echoed 32-bit word is

inverted. If set and using the OPEN Alliance SPI protocol for protected control read transactions, the

MS bit of each 32-bit complement word is inverted. If set and using the generic SPI protocol with

protection enabled, the CRC8 returned on a register read is inverted.

0x0

R/W

FIFO Sizes Register

Address: 0x3E, Reset: 0x00000464, Name: FIFO_SIZE

Before modifying the FIFO sizes, frame reception and transmission must be stopped and the FIFOs must be empty.

Configure the forwarding rules to drop all frames and set P1_UNK2HOST to 0 to ensure all received frames are dropped.

Use RXF_CLR & TXF_CLR to reset the FIFOs. Then, the FIFO sizes can be modified.

The total FIFO size must be less than or equal to 28 kB.

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