CY24488 datasheet(10/15 Pages) CYPRESS

Nome de Peças	CY24488

Descrição Electrónicos	Quad PLL Clock Generator with Serial Interface (I2C)

PDF	15 Pages

Scroll/Zoom	100%

Fabricante Electrônico	CYPRESS [Cypress Semiconductor]

Página de início	http://www.cypress.com

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10 / 15 page

CY24488

Document #: 001-09608 Rev. *A

Page 10 of 15

Serial Programming Interface Timing

Figure 6. Start and Stop Frame

Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)

SDAT

SCLK

START

Transition

to next Bit

STOP

SDAT

SCLK

DA6

DA5 DA0

R/W

ACK

RA7

RA6 RA1

RA0

ACK

STOP

START

ACK

Serial Programming Interface Timing Specifications

Parameter

Description

Min.

Max.

Unit

fSCLK

Frequency of SCLK

–

400

kHz

Start Mode Time from SDA LOW to SCL LOW

0.6

–

s

CLKLOW

SCLK LOW Period

1.3

–

s

CLKHIGH

SCLK HIGH Period

0.6

–

s

tSU

Data Transition to SCLK HIGH

100

–

tDH

Data Hold (SCLK LOW to data transition)

–

Rise Time of SCLK and SDAT

–

300

Fall Time of SCLK and SDAT

–

300

Stop Mode Time from SCLK HIGH to SDAT HIGH

0.6

–

s

Stop Mode to Start Mode

1.3

–

s

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